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1999
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Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect

9 years 5 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which employs the Elmore delay model for RC delay estimation and a crude repeater delay model. This approach, however, ignores an equally important aspect of interconnect optimization: transition time constraints at the sinks. More importantly, Elmore delay techniques because of their inherent inaccuracy are not suited to spec-based design which is directed towards synthesizing nets with user-specified delay/transition time requirements at the sinks. In this paper we present techniques for delay and transition time optimization for RC nets in the context of accurate moment-matching techniques for computing the RC delays and transition times, and an accurate driver/repeater delay model. The asymptotic increase in runtime over the Elmore delay model is O(q2 ) where q is the order of the moment-matching approximation. ...
Noel Menezes, Chung-Ping Chen
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1999
Where VLSID
Authors Noel Menezes, Chung-Ping Chen
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