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SAFECOMP
2000
Springer

Speeding-Up Fault Injection Campaigns in VHDL Models

10 years 6 months ago
Speeding-Up Fault Injection Campaigns in VHDL Models
Abstract. Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%.
B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reo
Added 25 Aug 2010
Updated 25 Aug 2010
Type Conference
Year 2000
Where SAFECOMP
Authors B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
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