Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

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This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor resides in the conﬁgurable logic, it can execute common genetic operators like crossover and mutation with a targeted data throughput of 420 MByte/s. Together with the microprocessor core, a complex evolutionary algorithm can be developed in software, but is processed at the speed of dedicated hardware.

Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me

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Coprocessor Architecture | ICES 2003 | Integrated Microprocessor Core | Microprocessor Core |

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Added	06 Jul 2010
Updated	06 Jul 2010
Type	Conference
Year	2003
Where	ICES
Authors	Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Meier, Johannes Schemmel, Felix Schürmann

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Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms

Coprocessor Architecture | ICES 2003 | Integrated Microprocessor Core | Microprocessor Core |

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