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ISCAS
2003
IEEE

Stable high-order delta-sigma DACS

13 years 9 months ago
Stable high-order delta-sigma DACS
— Stability analysis of high-order delta-sigma loops is a challenge. In this brief, a sufficient design criterion is presented for highorder multibit error-feedback DACs which are especially suitable for high-speed operation. This analytical criterion might be too conservative, but it allows the design of stable, robust, and high-resolution deltasigma DACs. Both analytical and numerical analysis are performed for verification. Also, experimental results of a discrete-component multiplier-free prototype demonstrate 10-bit operation at a very low oversampling ratio of 4.
Peter Kiss, Jesus Arias, Dandan Li
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCAS
Authors Peter Kiss, Jesus Arias, Dandan Li
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