STAMP: A Universal Algorithmic Model for Next-Generation Multithreaded Machines and Systems

We propose a generic algorithmic model called STAMP (Synchronous, Transactional, and Asynchronous MultiProcessing) as a universal performance and power complexity model for multithreaded algorithms and systems. We provide examples to illustrate how to design and analyze algorithms using STAMP and how to apply the complexity estimates to better utilize CMP(Chip MultiProcessor)-based machines within given constraints such as power.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Michel Dubois, Hyunyoung Lee, Lan Lin
• Keywords: Asynchronous MultiProcessing, Distributed And Parallel Computing, IPPS 2007, Model Called Stamp, Power Complexity Model