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2010

Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems

9 years 5 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the adaptive optimal reverse body-bias voltage. The adaptive optimal body-bias voltage is generated from the proposed leakage monitoring circuit, which compares the subthreshold current (ISUB) and the band-to-band tunneling (BTBT) current (IBTBT). The proposed circuit was simulated in HSPICE using 32-nm bulk CMOS technology and evaluated using ISCAS85 benchmark circuits at different operating temperatures (ranging from 25 C to 100 C). Analysis of the results shows a maximum of 551 and 1491 times leakage power reduction at 25 C and 100 C, respectively, on a circuit with 546 gates. The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits. In this approach, the temperature and supply voltage variations are c...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
Added 22 May 2011
Updated 22 May 2011
Type Journal
Year 2010
Where TIM
Authors HeungJun Jeon, Yong-Bin Kim, Minsu Choi
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