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PATMOS
2007
Springer

A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits

10 years 8 months ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern circuit designs may suffer from design uncertainties, unpredictable in the design phase or even after manufacturing. This paper presents an optimization technique to make pipeline circuits robust against delay variations and thus maximize timing yield. By trading larger flip-flops for smaller latches, the proposed approach can be used as a post-synthesis or post-layout optimization tool, allowing accurate timing information to be available. Experimental results show an average of 31% timing yield improvement for pipeline circuits. They suggest that our method is promising for high-speed designs and is capable of tolerating clock variations.
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia
Added 09 Jun 2010
Updated 09 Jun 2010
Type Conference
Year 2007
Where PATMOS
Authors Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jiang, Yao-Wen Chang
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