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DAC
1994
ACM

Statistical Delay Modeling in Logic Design and Synthesis

9 years 3 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circuits. In order to capture the impact of these variations on the delay behavior of these circuits we propose a pair of statistical delay models for use inlogicdesign. These models abstract the real variations from the process level and can be used for statistical delay analysis and optimization in logic design and synthesis while oering an eciency vs. accuracy tradeo.
Horng-Fei Jyu, Sharad Malik
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1994
Where DAC
Authors Horng-Fei Jyu, Sharad Malik
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