Statistical Fault Injection

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A method for Statistical Fault Injection (SFI) into arbitrary latches within a full system hardware-emulated model is validated against particle-beam-accelerated SER testing for a modern microprocessor. As performed on the IBM POWER6 microprocessor, SFI is capable of distinguishing between error handling states associated with the injected bit flip. Methodologies to perform random and targeted fault injection are presented. Keywords – Fault Injection, Soft Errors, SER, SFI

Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W.

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Computer Networks | DSN 2008 | Fault Injection | IBM POWER6 Microprocessor | Statistical Fault Injection |

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Added	29 May 2010
Updated	29 May 2010
Type	Conference
Year	2008
Where	DSN
Authors	Pradeep Ramachandran, Prabhakar Kudva, Jeffrey W. Kellington, John Schumann, Pia Sanda

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Statistical Fault Injection

Computer Networks | DSN 2008 | Fault Injection | IBM POWER6 Microprocessor | Statistical Fault Injection |

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