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DAC
2004
ACM

Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining

10 years 6 days ago
Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining
With deep-sub-micron (DSM) technology, statistical timing analysis becomes increasingly crucial to characterize signal transmission over global interconnect wires. In this paper, a novel statistical timing analysis approach has been developed to analyze the behavior of two important pipelined architectures for multiple clock-cycle global interconnect, namely, the flip-flop inserted global wire and the latch inserted global wire. We present analytical formula that is based on parameters obtained using Monte Carlo simulation. These results enable a global interconnect designer to explore design trade-offs between clock frequency and probability of bit-error during data transmission. Categories and Subject Descriptors B.8 [Hardware]: Performance and Reliability General Terms Algorithms, Performance, Design, Reliability Keywords Statistical Timing Analysis, Interconnect Pipelining
Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2004
Where DAC
Authors Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen
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