STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores

This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator applying vectors to the SoC test pins but rather as a target, a huge repository of 32-bits test data and control commands. The ATE is connected to the functional SoC external RAM controller interface. The only additional test component in the SoC is a P1500 test processor that converts test data into serial P1500 streams. This paper applies the STEPS methodology to SoCs containing a VCIcompliant interconnect, a microprocessor, P1500 compliant IP cores and an external RAM controller interface. Using the ITC02 SoC benchmarks a comparison is done between the STEPS architecture and a classical bus-based strategy.

• Type: Conference
• Year: 2004
• Where: DATE
• Authors: Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna
• Keywords: DATE 2004, External Ram Controller, Hardware, RAM Controller Interface, SoC Test Pins