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DAC
1994
ACM

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits

9 years 3 months ago
Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits
A stochastic global optimization approach is presented for transistor sizing in CMOS VLSI circuits. This is a direct search strategy for the best design among feasible ones, with the designer determining when the search is stopped. Through examples, we show the power of this technique in quickly obtaining very good designs, for skew minimization problems.
Sharad Mehrotra, Paul D. Franzon, Wentai Liu
Added 09 Aug 2010
Updated 09 Aug 2010
Type Conference
Year 1994
Where DAC
Authors Sharad Mehrotra, Paul D. Franzon, Wentai Liu
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