Structured and tuned array generation (STAG) for high-performance random logic

Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides a complete design solution from logic to layout for regularly structured circuits. The STAG circuit tuning constraints are a key component of the methodology. The tuning contraints first guide a SPICE-level tuner to a violation free region in the design space. Secondly, the tuning methodology provides flexibility for targeting a variety of design contraints and objectives. Design examples illustrate STAG’s ability for fast turnaround time as well as for high performance and timing critical random logic. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles General Terms Design, Performance Keywords Design Automation, Programmable Logic Arrays (PLAs)

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
• Keywords: Design, Design Methodology, GLVLSI 2007, Structured Design, VLSI