A Study of Design Efficiency with a High-Level Language for FPGAs

Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used for mapping computations to such architectures still require the knowledge about architectural details of the target device to extract efficiency. A study of the Mobius language and tools is presented in this paper, with a focus on generated hardware performance. A number of streaming and memory-intensive applications have been developed and the results have been compared with the corresponding implementations in VHDL and a behavioral hardware description language. Based upon experimental evidences, it is concluded that Mobius, a minimal parallel processing language targeted for reconfigurable architectures, enhances productivity in terms of design time and code maintainability without considerably compromising performance and resources.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Zain-ul-Abdin, Bertil Svensson
• Keywords: Distributed And Parallel Computing, Gate-level Glue Logic, IPPS 2007, Reconfigurable Computing Devices, Reprogrammable Processing Architectures