A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors

This paper presents an examination of different cache and processor configurations assuming transistor densities will continue to increase as they have in the past. While in the short term any additional transistors should clearly be put into increasing the size of on-chip first-level caches, as transistor counts increase above a certain level this is no longer holds true. As cache sizes increase, so does the difficulty of accessing the cache in a single-cycle. Context switches also present a potential problem. A trace-driven simulation-based study of a wide range of cache configurations and processor counts was performed, and the results are presented here. In order to compare different configurations, the concept of an Equivalent Cache Transistor is presented. We found that the access time of the first-level data cache proved critical; configurations with a small single-cycle access data cache consistently outperformed much larger 2-cycle access caches. In addition, it appears that ...

• Type: Conference
• Year: 1994
• Where: ISCA
• Authors: Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
• Keywords: Cache, Hardware, ISCA 1994, Processor Configuration, Transistors