Sub-threshold design: the challenges of minimizing circuit energy

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In this paper, we identify the key challenges that oppose subthreshold circuit design and describe fabricated chips that verify techniques for overcoming the challenges. Categories and Subject Descriptors B.7.1 [ICs]: Types and Design Styles General Terms Performance, Design, Reliability Keywords Sub-threshold digital circuits, low voltage memory, dynamic voltage scaling, process variations, sub-threshold logic

Benton H. Calhoun, Alice Wang, Naveen Verma, Anant

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Dynamic Voltage Scaling | ISLPED 2006 | Low Voltage Memory | Subthreshold Circuit Design |

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Added	14 Jun 2010
Updated	14 Jun 2010
Type	Conference
Year	2006
Where	ISLPED
Authors	Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha Chandrakasan

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Sub-threshold design: the challenges of minimizing circuit energy

Dynamic Voltage Scaling | ISLPED 2006 | Low Voltage Memory | Subthreshold Circuit Design |

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