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CGO
2005
IEEE

SWIFT: Software Implemented Fault Tolerance

13 years 9 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. However, these advances make processors more susceptible to transient faults that can affect correctness. While reliable systems typically employ hardware techniques to address soft-errors, software techniques can provide a lower-cost and more flexible alternative. This paper presents a novel, software-only, transient-fault-detection technique, called SWIFT. SWIFT efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs. SWIFT also provides a high level of protection and performance with an enhanced control-flow checking mechanism. We evaluate an implementation of SWIFT on an Itanium 2 which demonstrates exceptional fault coverage with a reasonable performance cost. Compared to the best known single-threaded approach utilizing an ECC memory sy...
George A. Reis, Jonathan Chang, Neil Vachharajani,
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where CGO
Authors George A. Reis, Jonathan Chang, Neil Vachharajani, Ram Rangan, David I. August
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