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JEC
2006

Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications

8 years 8 months ago
Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be attained through parallelization. The importance of adequate inter-core interconnect is also demonstrated. We discuss the impact of having multiple frequency and voltage domains on chip to reduce the power consumption where parallelization fails. Finally, we investigate how the ad-hoc selection of tile size that is currently used in most single-chip multi-core processors impacts the power consumption of these architectures.
John Oliver, Ravishankar Rao, Diana Franklin, Fred
Added 13 Dec 2010
Updated 13 Dec 2010
Type Journal
Year 2006
Where JEC
Authors John Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella
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