Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

13

ISSS
1996
IEEE

favoriteEmaildiscussreport

94views Hardware» more ISSS 1996»

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification

13 years 8 months ago

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification

Download www.scarpaz.com

Luca Benini, Patrick Vuillod, Claudionor Jos&eacut

Real-time Traffic

Hardware | ISSS 1996 |

claim paper

Related Content

» Translation Validation of HighLevel Synthesis

» High Level Synthesis from SimnML Processor Models

» A Design Methodology for the Exploitation of High Level Communication Synthesis

» Hardware Synthesis of Parallel Machines from SystemC

» Unlocking the design secrets of a 229 Gbs Rijndael processor

» Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Gra...

» Modeling Reconfigurable SystemsonChips with UML MARTE Profile An Exploratory Analysis

» ASIP design and synthesis for non linear filtering in image processing

» Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis ...

Post Info
More Details (n/a)

Added	07 Aug 2010
Updated	07 Aug 2010
Type	Conference
Year	1996
Where	ISSS
Authors	Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli

Comments (0)