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1995
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Synthesis of pipelined DSP accelerators with dynamic scheduling

9 years 6 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology is presented to synthesize high throughput DSP functions into accelerator processors containing a datapath of highly pipelined, bitparallel hardware units. Emphasis will be put on the de nition of a controller architecture that allows ecient run-time schedules of these DSP algorithms on such highly pipelined data paths. The methodology will be illustrated by means of an FFT butter y accelerator block. 1 Motivation Complexdigitalsystems such as the videophone terminal of gure 1 typically consist out of a heterogeneous mix of hardware blocks: processor cores, general purpose macro blocks, and dedicated accelerator processors. These accelerator blocks are required to execute high performant DSP functions such as motion estimation and DCT/IDCT functions. In this paper we will concentrate on the generation of s...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ISSS
Authors Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man
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