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DAC
2004
ACM

Synthesizing interconnect-efficient low density parity check codes

9 years 4 months ago
Synthesizing interconnect-efficient low density parity check codes
Error correcting codes are widely used in communication and storage applications. Codec complexity has usually been measured with a software implementation in mind. A recent hardware implementation of a Low Density Parity Check code (LDPC) indicates that interconnect complexity dominates the VLSI cost. We describe a heuristic interconnect-aware synthesis algorithm which generates LDPC codes that use an order of magnitude less wiring with little or no loss of coding efficiency. Categories and Subject Descriptors: B.6.3 Automatic Synthesis, E.4 Error Control Codes, G.2.2 Graph Algorithms. General Terms: Algorithms, Performance, Design.
Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Way
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2004
Where DAC
Authors Marghoob Mohiyuddin, Amit Prakash, Adnan Aziz, Wayne Wolf
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