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2010
IEEE

Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads

9 years 8 months ago
Synthesizing memory-level parallelism aware miniature clones for SPEC CPU2006 and ImplantBench workloads
Abstract—We generate and provide miniature synthetic benchmark clones for modern workloads to solve two pre-silicon design challenges, namely: 1) huge simulation time (weeks to months) when using complete runs of modern workloads like SPEC CPU2006 having trillions of instructions on pre-silicon design models 2) unavailability of access to their specific target applications for computer architects, as some of them are proprietary in nature and vendors hesitate to share them. We first provide a detailed characterization of the SPEC CPU2006 and the ImplantBench suites based on microarchitecture-independent metrics. Our metrics include the Memory Level Parallelism (MLP) of these workloads to estimate the burstiness of accesses to the main memory. Secondly, our proposed framework, that uses this characterized information (including MLP) to generate synthetic clones is explained and evaluated. We provide the synthetic clones generated for CPU2006 workloads for download and use. The effi...
Karthik Ganesan, Jungho Jo, Lizy K. John
Added 17 May 2010
Updated 17 May 2010
Type Conference
Year 2010
Where ISPASS
Authors Karthik Ganesan, Jungho Jo, Lizy K. John
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