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RSP
1999
IEEE

System Design Validation Using Formal Models

13 years 8 months ago
System Design Validation Using Formal Models
Formal methods are a nice idea, but the size and complexity of real systems means that they are impractical. We propose that a reasonable alternative to attempting to specify and verify the system in its entirety is to build and an abstract model(s) of aspects of the system that are perceived as important. Using a model will not provide proof of the system, but it can help to find shortcomings and errors at an early stage. Executing the model should also give a measure of confidence in the final product. Many systems today are built from communicating components so that the task of the developers is becoming fitting these components together to form the required system. We show how a formal model can be sympathetic to this type of architecture using our tool, RolEnact and explain how this may be related to a COM implementation.
Peter Henderson, Robert John Walters
Added 04 Aug 2010
Updated 04 Aug 2010
Type Conference
Year 1999
Where RSP
Authors Peter Henderson, Robert John Walters
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