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JPDC
2000

A System for Evaluating Performance and Cost of SIMD Array Designs

9 years 3 months ago
A System for Evaluating Performance and Cost of SIMD Array Designs
: SIMD arrays are likely to become increasingly important as coprocessors in domain specific systems as architects continue to leverage RAM technology in their design. The problem this work addresses is the efficient evaluation of SIMD arrays with respect to complex applications while accounting for operating frequency and chip area. The underlying issues include the size of the architecture space, the lack of portability of the test programs, and the inherent complexity of simulating up to hundreds of thousands of processing elements. The overall method we use is to combine architecture level and Electronic Design Automation (EDA) level modeling by using an EDA based tool to calibrate architectural simulations. The resulting system retains much of the high throughput of the architecture level simulator but also has accuracy similar to that of an early pass EDA synthesis and circuit simulation. The particular problem of computational cost of the architectural level simulation is addres...
Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais K
Added 19 Dec 2010
Updated 19 Dec 2010
Type Journal
Year 2000
Where JPDC
Authors Martin C. Herbordt, Jade Cravy, Renoy Sam, Owais Kidwai, Calvin Lin
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