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ISVLSI
2008
IEEE

System Level Design Space Exploration for Multiprocessor System on Chip

8 years 8 months ago
System Level Design Space Exploration for Multiprocessor System on Chip
Future embedded systems will integrate hundreds of processors. Current design space exploration methods cannot cope with such a complexity. It is mandatory to extend these methods in order to meet future design constraints. We believe one solution is to add a new design exploration step above current methods. This extension corresponds to an abstraction rising to provide designer with a restricted design space. We propose in this work to enrich the classical exploration approaches by a pre-exploration step which reduces the architecture design space. This new step i) simplifies ii) performs and iii) makes possible, for a complex application the architecture exploration for future tera-scale multiprocessor-based systems. This method drastically reduces the architecture space at a higher level of the design flow which mitigates the codesign complexity and enables the designer to explore a large set of architectures.
Issam Maalej, Guy Gogniat, Jean Luc Philippe, Moha
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where ISVLSI
Authors Issam Maalej, Guy Gogniat, Jean Luc Philippe, Mohamed Abid
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