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2006
IEEE

System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors

10 years 7 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chip (MPoPCs) represent the recent trend in this arena; they integrate the advantages of both software programmability and hardware reconfigurability. However, FPGAs consume more energy than ASICs. The lack of powerful tools and models to estimate and verify the energy consumption in the early stages of the design cycle exacerbates this problem. In this paper, we propose a system-level energy estimation model to accompany our design methodology for HERA (HEterogeneous Reconfigurable Architecture), a versatile reconfigurable MPoPC that we have implemented on Xilinx FPGAs. The model utilizes both physical-level measurements from a hardware component library and application statistics. Experiments with the parallel LU factorization of large sparse matrices show an average error in energy estimation of about 5.17%. ...
Xiaofang Wang, Sotirios G. Ziavras
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2006
Where ICCD
Authors Xiaofang Wang, Sotirios G. Ziavras
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