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EIT
2009
IEEE

System-level memory modeling for bus-based memory architecture exploration

9 years 6 days ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we propose a novel system-level approach to memory design, which was not yet well addressed in existing SLD methodologies. In particular, we extend the SpecC methodology by defining various odels at different levels of abstraction and a set of refinement rules that support fast and accurate memory architecture exploration. We demonstrate the experimental results using a case study in which we show the benefit of our approach.
Zhongbo Cao, Ramon Mercado, Diane T. Rover
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where EIT
Authors Zhongbo Cao, Ramon Mercado, Diane T. Rover
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