Sciweavers

Share
CODES
2006
IEEE

System-level power-performance trade-offs in bus matrix communication architecture synthesis

10 years 2 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customization of such architectures for an application requires the exploration of a large design space. Thus designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper we present an automated framework for fast system-level, application-specific, powerperformance trade-offs in bus matrix communication architecture synthesis. Our paper makes two specific contributions. First, we develop energy macro-models for system-level exploration of bus matrix communication architectures. Second, we incorporate these macromodels into a bus matrix synthesis flow that enables designers to efficiently explore the power-performance design space of different bus matrix configurations. Experimental results show that our ...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,
Added 10 Jun 2010
Updated 10 Jun 2010
Type Conference
Year 2006
Where CODES
Authors Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt
Comments (0)
books