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DATE
2009
IEEE

System-level process variability analysis and mitigation for 3D MPSoCs

9 years 6 months ago
System-level process variability analysis and mitigation for 3D MPSoCs
Abstract—While prior research has extensively evaluated the performance advantage of moving from a 2D to a 3D design style, the impact of process parameter variations on 3D designs has been largely ignored. In this paper, we attempt to bridge this gap by proposing a variability-aware design framework for fully-synchronous (FS) and multiple clock-domain (MCD) 3D systems. First, we develop analytical system-level models of the impact of process variations on the performance of FS 3D designs. The accuracy of the model is demonstrated by comparing against transistorlevel Monte Carlo simulations in SPICE - we observe a maximum error of only 0.7% (average 0.31% error) in the mean of the maximum critical path delay distribution. Second, to mitigate the impact of process variations on 3D designs, we propose a variability-aware 3D integration strategy for MCD 3D systems that maximizes the probability of the design meeting specified system performance constraints. The proposed optimization st...
Siddharth Garg, Diana Marculescu
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Siddharth Garg, Diana Marculescu
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