A systolic architecture for LMS adaptive filtering with minimal adaptation delay

Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents a systolic architecture with minimal adaptation delay and input/output latency, thereby improving the convergence behaviour to near that of the original LMS algorithm. The architecture is synthesized by using a number of bnction preserving transformations on the signal flow graph representation of the delayed LMS algorithm. With the use of carry-save arithmetic, the systolic folded pipelined architecture can support very high sampling rates, Eimited only by the delay of a full adder.

• Type: Conference
• Year: 1996
• Where: VLSID
• Authors: S. Ramanathan, V. Visvanathan
• Keywords: Adaptation Delay, Convergence Behaviour, Systolic Architecture, VLSI, VLSID 1996