A Tamper and Leakage Resilient von Neumann Architecture

An extended abstract of this paper is published in the proceedings of the 18th International Conference on Practice and Theory of Public-Key Cryptography—PKC 2015. This is the full version. A Tamper and Leakage Resilient von Neumann Architecture Sebastian Faust1 , Pratyay Mukherjee2 , Jesper Buus Nielsen2 , and Daniele Venturi3 2 Department of Computer Science, Aarhus University 1 Security and Cryptography Laboratory, EPFL 3 Department of Computer Science, Sapienza University of Rome February 18, 2015 We present a universal framework for tamper and leakage resilient computation on a von Neumann Random Access Architecture (RAM in short). The RAM has one CPU that accesses a storage, which we call the disk. The disk is subject to leakage and tampering. So is the bus connecting the CPU to the disk. We assume that the CPU is leakage and tamper-free. For a fixed value of the security parameter, the CPU has constant size. Therefore the code of the program to be executed is stored on the d...

• Type: Journal
• Year: 2015
• Where: PKC
• Authors: Sebastian Faust, Pratyay Mukherjee, Jesper Buus Nielsen, Daniele Venturi
• Keywords: Cryptology, PKC 2015