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MICRO
1998
IEEE

Task Selection for a Multiscalar Processor

10 years 4 months ago
Task Selection for a Multiscalar Processor
The Multiscalar architecture advocates a distributed processor organization and task-level speculation to exploit high degrees of instruction level parallelism (ILP) in sequential programs without impeding improvements in clock speeds. The main goal of this paper is to understand the key implications of the architectural features of distributed processor organization and task-level speculation for compiler task selection from the point of view of performance. We identify the fundamental performance issues to be: control flow speculation, data communication, data dependence speculation, load imbalance, and task overhead. We show that these issues are intimately related to a few key characteristics of tasks: task size, inter-task control flow, and inter-task data dependence. We describe compiler heuristics to select tasks with favorable characteristics. We report experimental results to show that the heuristics are successful in boosting overall performance by establishing larger ILP wi...
T. N. Vijaykumar, Gurindar S. Sohi
Added 05 Aug 2010
Updated 05 Aug 2010
Type Conference
Year 1998
Where MICRO
Authors T. N. Vijaykumar, Gurindar S. Sohi
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