Techniques for fast circuit simulation applied to power estimation of CMOS circuits

We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses stepwise equivalent conductance and piecewise linear waveform approximation. The power estimator has been implemented in the SWEC framework. Experimental results indicate that SWEC can obtain a substantial speed-up over HSPICE while maintaining an accuracy of within 5-7%. Benchmark results on a suite of industry circuits, which include circuits that HSPICE could not handle, are presented.

• Type: Conference
• Year: 1995
• Where: ISLPED
• Authors: Premal Buch, Shen Lin, Vijay Nagasamy, Ernest S. Kuh
• Keywords: Hardware, ISLPED 1995, Level Power Estimator, Power Estimator, Stepwise Equivalent Conductance