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DATE
2009
IEEE

Test architecture design and optimization for three-dimensional SoCs

9 years 6 months ago
Test architecture design and optimization for three-dimensional SoCs
Core-based system-on-chips (SoCs) fabricated on threedimensional (3D) technology are emerging for better integration capabilities. Effective test architecture design and optimization techniques are essential to minimize the manufacturing cost for such giga-scale integrated circuits. In this paper, we propose novel test solutions for 3D SoCs manufactured with die-to-wafer and die-to-die bonding techniques. Both testing time and routing cost associated with the test access mechanisms in 3D SoCs are considered in our simulated annealing-based technique. Experimental results on ITC’02 SoC benchmark circuits are compared to those obtained with two baseline solutions, which show the effectiveness of the proposed technique.
Li Jiang, Lin Huang, Qiang Xu
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Li Jiang, Lin Huang, Qiang Xu
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