Test generation for designs with multiple clocks

10 years 3 months ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize multiple clocks in the design effectively and efficiently in order to dramatically reduce test pattern count without sacrificing fault coverage or causing clock skew problem. This is achieved by pulsing multiple non-interactive clocks simultaneously and applying a clock concatenation technique. Experimental results on several industrial circuits show significant test pattern count reduction by using the proposed test generation procedures. Categories and Subject Descriptors B.8.1 Reliability, Testing, and Fault-Tolerance General Terms Algorithms, Design Keywords ATPG, Clock Domain, Scan Design
Xijiang Lin, Rob Thompson
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where DAC
Authors Xijiang Lin, Rob Thompson
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