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2009
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Test Input Generation Using UML Sequence and State Machines Models

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Test Input Generation Using UML Sequence and State Machines Models
We propose a novel testing approach that combines information from UML sequence models and state machine models. Current approaches that rely solely on sequence models do not consider the effects of the message path under test on the states of the participating objects. Dinh-Trong et al. proposed an approach to test input generation using information from class and sequence models. We extend their Variable Assignment Graph (VAG) based approach to include information from state machine models. The extended VAG (EVAG) produces multiple execution paths representing the effects of the messages on the states of their target objects. We performed mutation analysis on the implementation of a video store system to demonstrate that our test inputs are more effective than those that cover only sequence diagram paths.
Aritra Bandyopadhyay, Sudipto Ghosh
Added 24 May 2010
Updated 24 May 2010
Type Conference
Year 2009
Where ICST
Authors Aritra Bandyopadhyay, Sudipto Ghosh
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