Test Point Insertion: Scan Paths through Combinational Logic

We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability(DFT)overhead onarea or timingcan be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead forthe fullscan design. Wealsodiscuss its application to timing-driven partial scan design.

• Type: Conference
• Year: 1996
• Where: DAC
• Authors: Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
• Keywords: Computer Architecture, DAC 1996, Low-overhead Scan Design, Scan Design, Test Point Insertion