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DATE
2008
IEEE

Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs

10 years 5 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testing of multiple cores of a system-on-chip (SoC) in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. We present a test-scheduling technique for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. Simulation results are presented for two ITC’02 SoC benchmarks, and the proposed technique is compared with two baseline methods.
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DATE
Authors Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Richard Kacprowicz
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