Testing High-Speed SoCs Using Low-Speed ATEs

We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.

• Type: Conference
• Year: 2002
• Where: VTS
• Authors: Mehrdad Nourani, James Chin
• Keywords: Low-speed Ates, Overall Test Time, Test Methodology, VLSI, VTS 2002