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2002
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Testing High-Speed SoCs Using Low-Speed ATEs

10 years 3 months ago
Testing High-Speed SoCs Using Low-Speed ATEs
We present a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.
Mehrdad Nourani, James Chin
Added 16 Jul 2010
Updated 16 Jul 2010
Type Conference
Year 2002
Where VTS
Authors Mehrdad Nourani, James Chin
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