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ASPLOS
2009
ACM

Per-thread cycle accounting in SMT processors

11 years 5 months ago
Per-thread cycle accounting in SMT processors
This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they are running simultaneously on the SMT processor. This is done by accounting each cycle to either a base, miss event or waiting cycle component during multi-threaded execution. Single-threaded alone execution time is then estimated as the sum of the base and miss event components; the waiting cycle component represents the lost cycle count due to SMT execution. The cycle accounting architecture incurs reasonable hardware cost (around 1KB of storage) and estimates single-threaded performance with average prediction errors around 7.2% for two-program work
Stijn Eyerman, Lieven Eeckhout
Added 22 Nov 2009
Updated 22 Nov 2009
Type Conference
Year 2009
Where ASPLOS
Authors Stijn Eyerman, Lieven Eeckhout
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