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2015
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Thread-level parallelization and optimization of NWChem for the Intel MIC architecture

3 years 3 months ago
Thread-level parallelization and optimization of NWChem for the Intel MIC architecture
In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors’ greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant ...
Hongzhang Shan, Samuel Williams, Wibe de Jong, Leo
Added 16 Apr 2016
Updated 16 Apr 2016
Type Journal
Year 2015
Where PPOPP
Authors Hongzhang Shan, Samuel Williams, Wibe de Jong, Leonid Oliker
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