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FPL
2007
Springer

A Time-Triggered Network-on-Chip

13 years 9 months ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature for dependable real-time systems. A regular structured NoC with a pseudo-static communication schedule allows for a high bandwidth. In this paper we argue for a simple, time-triggered NoC structure to achieve maximum bandwidth. We have implemented the proposed TT-NoC in a low-cost FPGA. The base bandwidth is 29 Gbit/s and the peak bandwidth 230 Gbit/s for eight nodes. The idea is in line with current on-chip multiprocessor designs, such as the Cell processor. The simple design of the network and the network interface easies certification of the proposed NoC for safety critical applications.
Martin Schoeberl
Added 07 Jun 2010
Updated 07 Jun 2010
Type Conference
Year 2007
Where FPL
Authors Martin Schoeberl
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