Timing Analysis for Sensor Network Nodes of the Atmega Processor Family

Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor family used by Berkeley Motes lacks support for deriving safe bounds on the WCET, which is a prerequisite for performing real-time schedulability analysis. Our work fills this gap by providing an analytical method to obtain WCET bounds for this processor architecture. Our first contribution is to analyze both C and NesC code, the latter of which is unprecedented. The second contribution is to model control hazards and variable-cycle instructions, both handled more efficiently by our approach than by previous ones and results in up to 77% improvement in bounding the WCET. The results demonstrate that our timing analysis framework is able to tightly and safely estimate the WCET of the benchmarks while simulator results are shown to not always provide safe WCET bounds. While motivated by the Atmel Atmega series ...

• Type: Conference
• Year: 2005
• Where: RTAS
• Authors: Sibin Mohan, Frank Mueller, David B. Whalley, Christopher A. Healy
• Keywords: Atmega Processor Family, Atmel Atmega Processor, Real-Time Technology, RTAS 2005, WCET Bounds