A timing-driven module-based chip design flow

A Module-Rased design flow for digital ICs with hard and sofl modules is presented. Versions of the sofl modules are implemented with different areddelay characteristics. The versions represent flexibility that can he used in the physical design to meet timing requirements. The flow aims at minimizing the clobk cycle of the chip while providing quicker tum-around time. Unreliable wiring estimation is eliminated and costly iterations are reduced resulting in substantial reductions in tun time as well as a significantdecrease in the clock periods. Categories and Subject Descriptors General Terms Key\Gords J.6 [Computer-AidedEngineering] Algorithms, Performance, Design Design flow, Physical synthesis,Timing constraints

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Fan Mo, Robert K. Brayton
• Keywords: Computer Architecture, DAC 2004, Design Flow, Module-Rased Design Flow, Sofl Modules