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10

DAC
2005
ACM

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Timing-driven placement by grid-warping

13 years 6 months ago

Timing-driven placement by grid-warping

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Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chip surface on which the gates have been coarsely placed via a standard quadratic solve. In this paper, we introduce a timing-driven grid-warping formulation that incorporates slack-sensitivity-based net weighting. Given inevitable concerns about wirelength and runtime degradation in any timingdriven scheme, we also incorporate a more efficient net model and an integrated local improvement (“rewarping”) step. An implementation of these ideas, WARP2, can improve worst-case negative slack by 37% on average, with very modest increases in wirelength and runtime. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids-placement and routing. G.4 [Mathematical Software]: Algorithm Design and Analysis General Terms Algorithms, Design Keywords Algorithms, Placement

Zhong Xiu, Rob A. Rutenbar

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2-D Chip Surface | Computer Architecture | DAC 2005 | Slack-sensitivity-based Net Weighting | Standard Quadratic Solve |

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Added	13 Oct 2010
Updated	13 Oct 2010
Type	Conference
Year	2005
Where	DAC
Authors	Zhong Xiu, Rob A. Rutenbar

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