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2015
IEEE

Timing Driven Placement for Quasi Delay-Insensitive Circuits

3 years 5 months ago
Timing Driven Placement for Quasi Delay-Insensitive Circuits
—Asynchronous circuits offer promise in handling current and future technology scaling challenges. Unfortunately, their impact has been limited by the lack of design automation. We present A-NTUPLACE, a timing-driven placer uniquely suited to handling quasi delay-insensitive circuits. Our tool uses a generalization of repetitive event rule systems to identify critical signal transitions. The cell placement engine, based on a leading academic placer, NTUPlace3, incorporates net weights to minimize critical wirelengths as well as a novel balancing scheme to ensure isochronic fork constraints are met. We show that our placer is effective at both prioritizing selected nets and balancing forks, demonstrating improvements in 3 of our 4 benchmarks.
Robert Karmazin, Stephen Longfield Jr., Carlos Tad
Added 16 Apr 2016
Updated 16 Apr 2016
Type Journal
Year 2015
Where ASYNC
Authors Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar
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