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ICCD
1997
IEEE

TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model

13 years 7 months ago
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model
Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3MIPS using the Dhrystone V2.1 benchmark.
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Ta
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1997
Where ICCD
Authors Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
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