Sciweavers

Share
SPAA
2010
ACM

TLRW: return of the read-write lock

10 years 21 days ago
TLRW: return of the read-write lock
TL2 and similar STM algorithms deliver high scalability based on write-locking and invisible readers. In fact, no modern STM design locks to read along its common execution path because doing so would require a memory synchronization operation that would greatly hamper performance. In this paper we introduce TLRW, a new STM algorithm intended for the single-chip multicore systems that are quickly taking over a large fraction of the computing landscape. We make the claim that the cost of coherence in such single chip systems is down to a level that allows one to design a scalable STM based on readwrite locks. TLRW is based on byte-locks, a novel read-write lock design with a low read-lock acquisition overhead and the ability to take advantage of the locality of reference within transactions. As we show, TLRW has a painfully simple design, one that naturally provides coherent state without validation, implicit privatization, and irrevocable transactions. Providing similar properties in ...
David Dice, Nir Shavit
Added 18 Jul 2010
Updated 18 Jul 2010
Type Conference
Year 2010
Where SPAA
Authors David Dice, Nir Shavit
Comments (0)
books