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DATE
2007
IEEE

Toward a scalable test methodology for 2D-mesh Network-on-Chips

11 years 11 months ago
Toward a scalable test methodology for 2D-mesh Network-on-Chips
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clockspeed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.
Kim Petersén, Johnny Öberg
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DATE
Authors Kim Petersén, Johnny Öberg
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