Towards an optimised VLSI design algorithm for the constant matrix multiplication problem

The efficient design of multiplierless implementa- The goal is to find the optimal sub-expressions across all N dot tions of constant matrix multipliers is challenged by the huge products in (3) that lead to the fewest adder resources needed. solution search spaces even for small scale problems. Previous ap- Three properties aid the classification of approaches: SD proaches tend to use hill-climbing algorithms risking sub-optimal . . results. The proposed algorithm avoids this by exploring parallelpsteg a solutions. The computational complexity is tackled by modelling 1) SD Permutation: Consider that each of the N x N M-bit the problem in a format amenable to genetic programming and fixed point constants ai3 have a finite set of possible SD rephardware acceleration. Results show an improvement on state of resentations. For example with M = 4 the constant (-3)10 can the art algorithms with future potential for even greater savings, be represented as either (0011)2, (0101)2(1101)2, (0111...

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Andrew Kinane, Valentin Muresan, Noel E. O'Connor
• Keywords: Constant Matrix Multipliers, Fewest Adder Resources, ISCAS 2006, SD Rephardware Acceleration